The Physical Design & Static Timing Analysis (STA) internship gives you hands-on exposure to the backend VLSI design flow. Learn floorplanning, placement, routing, and timing closure techniques used in modern semiconductor design projects. This comprehensive program spans **144 hours** of in-depth training and project work.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
What makes this Physical Design internship valuable for your backend VLSI career.
This internship is ideal for passionate learners ready to dive into semiconductor design.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Aspiring to start a career in VLSI design
Working Professionals
Looking to upskill in VLSI design
Programming Background
Basic coding knowledge in HDL/Verilog is beneficial
This **144-hour** program is structured to provide deep technical expertise and professional readiness, combining the entire backend VLSI flow with essential program features.
End-to-end understanding and hands-on implementation of the full physical design flow from netlist to GDSII.
Learn core placement, macro placement, pin assignment, power planning (IR Drop/EM), and congestion management for optimized layouts.
Design, implement, and analyze clock trees (HFNS vs. CTS) for timing closure, power, and useful skew techniques.
Implement global and detailed routing strategies while addressing DRCs, LVS, Open/Shorts, Antenna violations, crosstalk, and IR drop.
Perform comprehensive Setup/Hold analysis and fixing, generate SPEF, and execute signoff using industry-standard tools like Tempus.
Gain hands-on expertise with Cadence Innovus, Synopsys Genus, Tempus, and advanced TCL scripting for design automation and issue fixing.
Work on mini physical design projects simulating actual chip layout and timing closure challenges under expert mentorship.
Mock interviews, technical assessments, project reviews, and job opportunities with partner semiconductor industries to ensure placement readiness.
A week-by-week breakdown of the topics covered in our Physical design and STA internship.
| Week | Topic | Topic Details |
|---|---|---|
| Week-1 | Unix Essentials – Basics | Basic Unix commands. Linux OS introduction. Hands-on practice. Gvim editor introduction and basic commands. |
| Week-2 | Unix Advanced & Gvim | Advanced Unix commands (find, grep, awk, sed, etc.). Hands-on labs using Linux OS. Gvim editor advanced usage. |
| Week-3 | TCL Basics & PD CMOS Basics – Part 1 | TCL: Basic input/output commands, variables, conditional statements, loops. PD CMOS: CMOS power and delay factors. |
| Week-4 | TCL Advanced & PD CMOS Basics – Part 2 | TCL: List and string operations, file handling. PD CMOS: CMOS fabrication steps, CMOS layout, FEOL and BEOL layers. |
| Week-5 | ASIC Design Flow & STA – Part 1 | Detailed ASIC design flow. Introduction to Physical Design. Clock concepts and types of clocks. |
| Week-6 | STA – Part 2 | Clock latency, skew, and uncertainty. Setup and Hold analysis. In-to-Reg and Reg-to-Out paths. Example problems. |
| Week-7 | Synthesis & PD Input Files – Part 1 | Inputs for synthesis. Synthesis flow. Logic optimization techniques. Hands-on labs using Genus tool. |
| Week-8 | Synthesis & PD Input Files – Part 2 | Analysis of synthesis reports. PD input files: Liberty, LEF, Tech LEF, Netlist, MCMM. Import design into Innovus tool. |
| Week-9 | Floorplanning – Part 1 | Partitioning. Full-chip vs block-level design. Die/core area estimation. Aspect ratio and utilization. |
| Week-10 | Floorplanning – Part 2 | IO placement guidelines. Efficient macro placement. Physical-only cell placement and verification. |
| Week-11 | Power Planning & Innovus Automation | IR drop and Electromigration. Power planning structures. Fixing power planning issues. Innovus legacy and stylus modes. |
| Week-12 | Innovus Automation – Advanced | Objects, attributes, attribute values. dbGet and dbSet commands. Writing TCL automation programs. |
| Week-13 | Placement | Pre-placement checks. Placement constraints. Timing-driven and congestion-driven placement. Congestion analysis and fixes. |
| Week-14 | CTS & Routing | HFNS vs CTS. CTS constraints and exceptions. Routing concepts. DRC, antenna, opens/shorts analysis and fixes. |
| Week-15 | Timing Closure & ECO Automation | TCL automation for timing analysis. SPEF extraction. Tempus inputs. DRV, Setup & Hold fixing. ECO generation and implementation in Innovus. |
Enroll in our internship program and become a backend VLSI design professional. Limited seats available!
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