The Custom Analog Layout Design internship provides intensive hands-on experience in designing and optimizing analog and mixed-signal layouts. Learn transistor-level layout, parasitic extraction, and matching techniques critical for precision analog ICs. This is a comprehensive **12-Week, 100+ Hours** program focused on sign-off ready analog IP design.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
Why this Analog Layout internship is a great investment for your career.
This internship is ideal for passionate learners ready to dive into semiconductor design.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Aspiring to start a career in VLSI design
Working Professionals
Looking to upskill in VLSI design
Programming Background
Basic coding knowledge in HDL/Verilog is beneficial
This 12-week program is designed to deliver industry-ready expertise for custom analog layout roles, focusing on sign-off skills.
Master the complete flow: Schematic → Layout → DRC → LVS → PEX → Simulation for sign-off ready circuits.
Create layouts for basic devices, multi-finger MOS, current mirrors, differential pairs, poly resistors, and MOS/MOM capacitors with a focus on matching and symmetry.
Learn hierarchical layout, block-level floorplanning, power routing, guarding, shielding, and parasitic-aware routing.
Perform comprehensive verification using industry tools (Assura/PVS/Quantus) to ensure fabrication readiness.
Develop skills to optimize layout for reduced parasitics, improved matching, and performance (e.g., gain, offset, speed).
Complete a full analog IP layout project (Op-Amp/Comparator) using Cadence Virtuoso/Custom Compiler under expert mentorship.
A week-by-week breakdown of the topics covered in our Custom Analog Layout Design internship, culminating in a sign-off ready project.
| Week | Topic | Topic Details / Hands-on / Mini-Project |
|---|---|---|
| WEEK 1 | Introduction & Foundations | Overview of schematic-to-layout flow, MOS basics, W/L sizing, tool environment. Mini-Project: CMOS inverter layout, DRC & LVS. |
| WEEK 2 | Basic Devices & Layout Rules | Transistor orientation, contacts, vias, enclosure rules. Hands-on: Multi-finger MOS layout. |
| WEEK 3 | Analog Building Blocks | Current mirrors, differential pairs, matching and symmetry techniques. |
| WEEK 4 | Passive Components Layout | Poly resistors, MOM capacitors, guard rings, shielding techniques. |
| WEEK 5 | Sub-Block Layout Practice | Biasing networks, simple OTA and comparator sub-blocks. |
| WEEK 6 | Floorplanning & Hierarchical Layout | Block floorplanning, placement strategies, power routing. |
| WEEK 7 | Full Block Layout – Part 1 | Start full analog block layout, placement, matching, initial routing. |
| WEEK 8 | Full Block Layout – Part 2 | Final routing, power integrity, area optimization, metal density. |
| WEEK 9 | Parasitic Extraction (PEX) | Run extraction, analyze parasitic impact, pre vs post-layout simulation. |
| WEEK 10 | Layout Optimization | Mismatch reduction, parasitic minimization, performance optimization. |
| WEEK 11 | Final Integration & Sign-off | DRC, LVS, PEX, ERC, antenna checks, GDS generation. |
| WEEK 12 | Final Project + Documentation | Complete project deliverables, final PPT and technical report. |
| WEEK 13 | Advanced Layout & Reliability | Latch-up prevention, ESD rules, antenna effects, reliability-aware layout. |
| WEEK 14 | Industry Tape-out Flow & Debugging | Foundry checks, debugging strategies, ECO concepts. |
| WEEK 15 | Interview Readiness & Portfolio | Interview preparation, portfolio building, mock presentations. |
Join our internship to become a professional in analog/mixed-signal layout design. Limited seats available!
Apply Now