The Design for Testability (DFT) internship is a comprehensive **12-Week, 100+ Hours** program designed to provide an in-depth, hands-on understanding of test methodologies used in modern chip design. Participants will master the complete DFT flow, from scan insertion and ATPG pattern generation to fault analysis and sign-off, using industry-standard Cadence tools.
Reasons to invest in your VLSI career with us.
Learn from industry veterans with 10+ years of experience at top semiconductor Industries.
80% practical, 20% theory - focus on hands-on skills and real-world applications.
Limited participants ensure personalized attention and one-on-one mentoring.
Full access to professional simulators and debugging tools for your projects.
What makes this DFT internship impactful for your VLSI career.
Perfect for students and professionals aiming to specialize in chip testing and DFT.
B.Tech / M.Tech Students
ECE, EEE, VLSI, and related disciplines
Fresh Graduates
Interested in starting a DFT-based VLSI career
Working Professionals
Looking to upskill in chip testing and validation
Technical Background
Basic knowledge of digital electronics and Verilog preferred
Achieve the overall objective of implementing a full DFT flow with industry-standard Cadence tools, culminating in a sign-off ready project.
Master the complete Cadence-based DFT Flow: from fault modeling and scan insertion to ATPG generation and pattern simulation.
Insert Full Scan Chains using **Modus DFT**, configure architecture, handle multi-clock domains, and optimize via Chain Reordering and Lock-up Latches.
Generate ATPG patterns for **Stuck-at** and **Transition (Delay)** faults, analyze Fault Coverage, and debug untestable logic (TPI/Redundancy).
Understand the need for compression, implement compression logic (X-masking), and grasp the fundamentals of Memory Built-In Self-Test (MBIST).
Simulate patterns using **Xcelium** (Gate-Level Simulation) with SDF back-annotation, and perform final DFT checks for sign-off.
Hands-on proficiency with Cadence Modus DFT, Xcelium Simulator, and an understanding of interaction with Genus/Innovus for physical aware DFT.
A week-by-week breakdown of the topics covered in our Design for Testability internship.
| Week | Topic | Topic Details / Hands-on |
|---|---|---|
| WEEK 1 | DFT Basics + Cadence Tool Flow | DFT motivation & need, Manufacturing defects overview, Fault Models: SA, Transition, Bridging, Delay, Cadence DFT ecosystem overview. Hands-on: Cadence environment setup, Launch Genus, Modus & Xcelium. |
| WEEK 2 | Scan Fundamentals | Scan FF, Scan MUX, Scan enable & modes, Controllability & Observability, Scan design rules. Hands-on: Replace FF → Scan FF manually, Create single scan chain, Run Genus DRC. |
| WEEK 3 | Scan Insertion – Genus Basics | Genus scan insertion flow, Scan configuration options, Clock & reset handling. Hands-on: Full scan insertion using Genus, Analyze scan reports (Chain length, number of chains, lock-up latches). |
| WEEK 4 | Scan Optimization & Stitching | Chain reordering concepts, Multi-clock scan issues, Lock-up latches & timing. Hands-on: Reorder scan chains, Insert lock-up latches, Validate scan connectivity. |
| WEEK 5 | ATPG Fundamentals (Stuck-at) | Introduction to ATPG, Fault list generation, SA ATPG algorithms. Hands-on: Run SA ATPG in Modus, Generate Verilog/STIL patterns, Analyze test coverage. |
| WEEK 6 | Transition ATPG (TDF) | LOS vs LOC methods, Timing constraints for ATPG, Multi-clock delay testing. Hands-on: Generate transition ATPG patterns, Compare SA vs Transition results. |
| WEEK 7 | ATPG Pattern Simulation | Pattern simulation flow, Behavioural vs Gate-level simulation. Hands-on: Setup Xcelium for ATPG simulations, Apply WGL/STIL patterns, Debug simulation mismatches. |
| WEEK 8 | Test Compression – Concepts & Flow | Need for compression, Compressor/decompressor logic, X-masking techniques. Hands-on: Insert compression logic, Generate compressed patterns, Compare pattern reduction, Run Modus compression reports. |
| WEEK 9 | Compression ATPG & Simulation | Compression ATPG flow, Tester data volume reduction, Debug compressed patterns. Hands-on: Simulate compressed patterns, Analyze coverage impact. |
| WEEK 10 | Test Coverage Analysis | Untestable faults, Redundant logic, Coverage improvement strategies. Hands-on: Improve coverage for sample design, Insert observation/control points, Coverage comparison (Pre vs Post TPI). |
| WEEK 11 | Test Point Insertion (TPI) | Control vs Observe points, When & where to insert TPI, Impact on area/timing. Hands-on: Insert TPIs in Modus, Re-run ATPG. |
| WEEK 12 | Hierarchical & Full-Chip DFT | Hierarchical DFT flow, Black-box handling, Multi-voltage domain challenges. Hands-on: Integrate multiple modules, Insert scan at top level, Run top-level ATPG, Validate complete DFT flow. |
| WEEK 13 | DFT + Physical Design Interaction | DFT-aware synthesis (Genus), Placement impact on scan, Physical-aware DFT concepts, Review scan with physical constraints. |
| WEEK 14 | DFT Sign-off & Documentation | DFT sign-off checklist, ATPG sign-off metrics. Hands-on: Final DFT rule check, Run all ATPG types, Generate final WGL/STIL files, Sign-off coverage & reports. |
| WEEK 15 | Final Project + Review | Project execution, Presentation & reporting, Industry interview discussion. Project Options: Full Scan + ATPG + GLS, Compression-based DFT, DFT coverage improvement, Multi-clock DFT design, Hierarchical DFT project. |
Join our specialized DFT internship program and become job-ready in semiconductor testing. Limited seats available!
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